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import NvRules

def get_identifier():
    return "MemoryL2Compression"

def get_name():
    return "Memory L2 Compression"

def get_description():
    return "Detection of inefficient use of L2 Sparse Data Compression"

def get_section_identifier():
    return "MemoryWorkloadAnalysis_Chart"

def apply(handle):
    ctx = NvRules.get_context(handle)
    action = ctx.range_by_idx(0).action_by_idx(0)
    fe = ctx.frontend()

    cc_major = action.metric_by_name("device__attribute_compute_capability_major").as_uint64()
    cc_minor = action.metric_by_name("device__attribute_compute_capability_minor").as_uint64()
    cc = cc_major * 10 + cc_minor

    if 80 <= cc:
        compInputSectors = action.metric_by_name("lts__gcomp_input_sectors.sum").as_double()
        if 0.0 < compInputSectors:
            compInputBytes = 32.0 * compInputSectors
            compSuccessRate = action.metric_by_name("lts__average_gcomp_input_sector_success_rate.pct").as_double()

            # Check for low success rate
            if compSuccessRate < 20:
                message = "Out of the {:.1f} bytes sent to the L2 Compression unit only {:.2f}% were successfully compressed. To increase this success rate consider marking only those memory regions as compressible that contain the most zero values and/or expose the most homogeneous values.".format(compInputBytes, compSuccessRate)
                fe.message(NvRules.IFrontend.MsgType_MSG_WARNING, message, "Low Compression Rate")

            l1WriteBytes = action.metric_by_name("l1tex__m_l1tex2xbar_write_bytes.sum").as_double()
            # Check for write access pattern
            if 4.0 * l1WriteBytes < compInputBytes:
                message = "The access patterns for writes to compressible memory are not well suited for the L2 Compression unit. As a consequence, {:.1f}x the data written to the L2 cache has to be communicated to the L2 Compression unit. Try maximizing local coherence for the write operations to compressible memory. For example, avoid writes with large strides as they lead to partial accesses to many L2 cache lines. Instead, try accessing fewer overall cache lines by modifying many values per cache line with each warp's execution of a write operation.".format(compInputBytes/l1WriteBytes)
                fe.message(NvRules.IFrontend.MsgType_MSG_WARNING, message, "Access Pattern")